Hercules instruction times from s370_perf - a first analysis and observations

A first fully analyzed instruction timing dataset for my Intel Xeon E5-1620 reference system is now available under the case id 2018-03-31_sys2 in the GitHub project wfjm/s370-perf. The page contains a list of findings.

Up front a proviso: there are significant deviations from a simple additive instruction timing model. See section additivity of instruction times.

Some findings simply show nicely how an emulator like Hercules works, e.g.

Other key findings are

The poor CLCL performance, when compared to CLC, is a bit surprising because MVCL shows roughly the same performance as MVC, so the overhead of an interruptible instruction can't be the culprit.

Any remarks and comments are very welcome.

Data for many other systems is available now, see list of cases, but the full analysis will take some time.

2018-12-27: MVCIN, CLCL and TRT performance significantly improved in Hercules Release V4.1, see this short note.
For original posting to Yahoo! Group - Hercules-390 see topic 83415.