Fig F-1: A KB11-C processor without FPP and one Massbus interface, build around 1976 in SN74Sxx Schottky TTL technology. The w11a core has a similar feature set. See also hi-res jpg, and view on backplane in wire wrap technology. Picture courtesy of Dave McGuire, see also Dave's PDP-11/70 site.
Fig F-2: PDP-11/70 Console with 2 RK05 drives with a UNIX 7th edition system (see disk labels in high resolution jpg). The current w11a systems emulate a similar configuration. Picture courtesy of John Holden. See also John's PDP-11 Site.
Fig F-3: w11a running on a Digilent Nexys2 board. The board is powered over USB. FPGA configuration as well as the rlink connection can be done via the Cypress FX2 USB controller available on the Nexys2. Alternatively, the rlink connection can be done via the RS232 port and a FTDI US232R-100 cable. (wfjm cc-by-4.0)

The w11a CPU core

The w11a CPU core has a functionality very close to a PDP-11/70 CPU (Model KB11-B or KB11-C) and supports with very few exceptions everything the PDP-11 architecture has to offer:

All fits today easily in a fraction of a modest size low cost FPGA. The original 11/70 CPU was implemented in TTL, see Figure F-1 for comparison.

The I/O System

Project goal was to create a retro-computing platform able to run the historical UNIX systems and other original software. The I/O system is therefore setup to have the same register model and semantics as the original DEC UNIBUS peripherals. To interface this to contemporary I/O hardware all I/O transactions are emulated by a backend server in the following way:

Currently available is a basic set of UNIBUS peripherals which is, apart from the IIST, quite similar to a full configuration of the early '80ties:

Complete Systems

The project holds all the sources to synthesize a complete system. The systems are comprised of

Complete configurations for nine boards are currently part of the project, seven are FPGA verified, two are only simulation verified:

  Name              Board       FPGA      Clk   Mem  --- Resource Usage --- Veri
                                          MHz    kB   flop  luts  slices
  sys_w11a_c7       Cmod A7     XC7A35T    80   672   3369  7279  2099(26%) FPGA
  sys_w11a_as7      Arty S7     XC7S50     75  3840   6843 11480  3425(43%) sim
  sys_w11a_arty     Arty A7     XC7A35T    72  3840   6838 11497  3392(42%) FPGA
  sys_w11a_b3       Basys3      XC7A35T    80   176   2968  6633  1963(24%) FPGA
  sys_w11a_n4d      Nexys A7    XC7A100T   80  3840   6850 11174  3563(22%) FPGA
  sys_w11a_n4       Nexys4      XC7A100T   80  3840   3418  7272  2234(14%) Note 1
  sys_w11a_n3       Nexys3      XC6SLX16   64  3840   3167  6314  2130(93%) FPGA
  sys_w11a_n2       Nexys2      XC3S1200E  52  3840   3219  9886  5796(66%) FPGA
  sys_w11a_s3       S3board     XC3S1000   50  1024   3019  9338  5558(72%) Note 2

  legacy BRAM only versions
  sys_w11a_br_as7   Arty S7     XC7S50     80   256   2821  6479  1887(23%) sim
  sys_w11a_br_arty  Arty A7     XC7A35T    80   176   2829  6499  1897(23%) FPGA
  sys_w11a_br_n4d   Nexys A7    XC7A100T   80   512   3137  7061  2125(13%) FPGA

    Note 1: Board failed in July 2019. FPGA tested before, since then only sim tested
    Note 2: Board available but effectively retired

The Digilent Nexys2, Nexys3 and Nexys4 boards have 16 MByte PSRAM (mt45w8mw16b) of which only 4 MByte, the maximum a PDP-11 can address, are used. The Digilent Cmod A7 has a 512 kByte SRAM (is61lv25616), which is extended by 160 kByte from BRAM. The Digilent S3board has 1 MByte SRAM (is61lv2561). The Digilent Basys3 has no memory external to the FPGA. The memory seen by the w11a core is build from BRAMs, with a total size of 176 kB. The DDR memory on the Digilent Arty A7, Arty S7, and Nexys A7 is now supported. In addition, designs which use only the BRAMs are provided and offer limited memory visible to the w11a core.

System Configuration

All systems have the following configuration for the UNIBUS peripherals:

  Controller Name                    CSR  VEC PRI    Device Names
                                                     BSD     DEC
  IIST    MP interrupt/timer      177500  260  6     -       -         optional
  KW11-P  programmable clock      172540  104  6     -       -
  KW11-L  line frequency clock    177546  100  6     -       -
  RL11    disk controller         174400  160  5     rlxh    DLx:      (x=0..3)
  RK11    disk controller         177400  220  5     rkxh    DKx:      (x=0..7)
  RH/RP   disk controller         176700  254  5     xpxa    DBx:,DRx: (x=0..3)
  TM11    tape controller         172520  224  5     mt      MTx:      (x=0..3)
  DEUNA   ethernet interface      174510  120  5     de 0    XE0:
  DL11    console                 177560  060  4     cn 0    YL0:
  DL11    2nd console             176500  300  4     ttyl 1  YL1:
  DZ11    terminal interface      160100  310  5     tty *   YZx:      (x=0..7)
  PC11    papertape read/punch    177550  070  4     -       PP:,PR:
  LP11    line printer            177514  200  4     lp 0    LP:

  devices yet to be implemented:
  CR11    card reader             177160  230  6     -       CR:
  DU11    synchronous interface   160120  320  5     -       XU:
  DMC11   interprocessor link     160140  330  5     dmc     XM: