Fig F-1: A KB11-C processor without FPP and one Massbus interface, build around 1976 in SN74Sxx Schottky TTL technology. The w11a core has a similar feature set. See also hi-res jpg, and view on backplane in wire wrap technology. Picture courtesy of Dave McGuire, see also Dave's PDP-11/70 site.
Fig F-2: PDP-11/70 Console with 2 RK05 drives with a UNIX 7th edition system (see disk labels in high resolution jpg). The current w11a systems emulate a similar configuration. Picture courtesy of John Holden. See also John's PDP-11 Site.
Fig F-3: w11a running on a Digilent Nexys2 board. The board is powered over USB. FPGA configuration as well as the rlink connection can be done via the Cypress FX2 USB controller available on the Nexys2. Alternatively, the rlink connection can be done via the RS232 port and a FTDI US232R-100 cable.

The w11a CPU core

The w11a CPU core has a functionality very close to a PDP-11/70 CPU (Model KB11-B or KB11-C) and supports with very few exceptions everything the PDP-11 architecture has to offer:

All fits today easily in a fraction of a modest size low cost FPGA. The original 11/70 CPU was implemented in TTL, see Figure F-1 for comparison.

The I/O System

Project goal was to create a retro-computing platform able to run the historical UNIX systems and other original software. The I/O system is therefore setup to have the same register model and semantics as the original DEC UNIBUS peripherals. To interface this to contemporary I/O hardware all I/O transactions are emulated by a backend server in the following way:

Currently available is a basic set of UNIBUS peripherals which is, apart from the IIST, quite similar to a baseline configuration of the late '70ties and early '80ties:

Complete Systems

The project holds all the sources to synthesize a complete system. The systems are comprised of

Complete configurations for five boards are currently part of the project:

  Name              Board       FPGA       Clock  Memory  --- Resource Usage ---
                                           [MHz]    [kB]   flop  luts  slices
  sys_w11a_br_arty  Arty        XC7A35T      80      176   2226  5217  1603(20%)
  sys_w11a_b3       Basys3      XC7A35T      80      176   2361  5326  1615(20%)
  sys_w11a_br_n4d   Nexys4 DDR  XC7A100T     80      512   2491  5473  1728(11%)
  sys_w11a_n4       Nexys4      XC7A100T     80     3840   2566  5593  1759(11%)
  sys_w11a_n3       Nexys3      XC6SLX16     64     3840   2671  5166  1875(82%)
  sys_w11a_n2       Nexys2      XC3S1200E    52     3840   2689  8248  4819(55%)
  sys_w11a_s3       S3board     XC3S1000     50     1024   2551  7943  4668(60%)

The Digilent Nexys2, Nexys3 and Nexys4 boards have 16 MByte PSRAM (mt45w8mw16b) of which only 4 MByte, the maximum a PDP-11 can address, are used. The Digilent S3board has 1 MByte SRAM (is61lv2561). The Digilent Basys3 has no memory external to the FPGA. The memory seen by the w11a core is build from BRAMs, with a total size of 176 kB. The DDR memory on the Digilent Arty, and Nexys4 DDR is not yet supported. Designs which use, like for Basys3, the BRAMs are provided and offer limited memory visible to the w11a core.

System Configuration

All systems have the following configuration for the UNIBUS peripherals:

  Controller Name                    CSR  VEC PRI    Device Names
                                                     BSD     DEC
  IIST    MP interrupt/timer      177500  260  6     -       - 
  KW11-L  line frequency clock    177546  100  6     -       - 
  RL11    disk controller         174400  160  5     rlxh    DLx:      (x=0..3)
  RK11    disk controller         177400  220  5     rkxh    DKx:      (x=0..7)
  RH/RP   disk controller         176700  254  5     xpxa    DBx:,DRx: (x=0..3)
  TM11    tape controller         172520  224  5     mt      MTx:      (x=0..3)
  DL11    console                 177560  060  4     cn 0    TT0:
  DL11    2nd console             176500  300  4     cn 1    TT1:
  PC11    papertape read/punch    177550  070  4     -       PP:,PR:
  LP11    line printer            177514  200  4     lp 0    LP: