Description
The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10) and a rather complete set of UNIBUS peripherals (DL11, LP11, PC11, and DEUNA), and last but not least a cache and memory controllers for SRAM, PSRAM, and SDRAM (via Xilinx MIG core).
The design is FPGA proven, runs currently on Digilent Cmod A7 , Arty A7 , Basys3 , Nexys4 , Nexys3 , Nexys2 and S3board boards. Implementations for Digilent Arty S7 and Nexys4 DDR are provided too, but are only simulation tested. See section Complete Systems for more information.
5th Edition UNIX, 7th Edition UNIX, and 2.11BSD UNIX are known to boot, the hardware should also support DEC RT11 and RSX-11M, see section Running Systems for more information.
This is a retrocomputing project, rebuilding hardware from the late 70s and running historical software. To get into the tune see Figure D-1, a 11/70 console, and Figure F-2, a baseline system setup.
Detailed Information
For more details see the sections:
- Status: Systems and Issues, Releases, Statistics, Roadmap, Credits
- Implementation: Features, Architecture, Performance, Verification, Directory Layout, Source Code View
- Installation: Downloads, Build System, System Images
- Resources: DEC Manuals, DEC Patents, Papers, Other Implementations
Latest News
For project news look into the w11 blog, the latest items are:
- 2018-10-14: KW11-P Programmable Clock Added - KW11-P Programmable Clock Added
- 2018-09-01: vivado 2018.2 much slower than 2017.2 - vivado 2018.2 much slower than 2017.2 Detecting the problem (2018-08-26) I s...
- 2016-12-11: w11 project moved to GitHub - To say something nice first: OpenCores is a very nice directory service f...
Related Projects
The work on the CPU and SoC triggered several related activities
Major Milestones
Being a 'leisture time project' things evolve at a modest pace. Key milestone so far were:
| Date | Milestone |
|---|---|
| Jan-2019 | Vivado Memory Interface Generator support added, w11a systems use now the DDR memory on Arty and Nexys4 DDR boards. |
| Aug-2018 | added Digilent Cmod-A7 port of w11a added, the so far lowest cost system. |
| Jun-2017 | added DEUNA Ethernet controller; functionally restricted, allows 2.11BSD with full networking. |
| Dec-2016 | moved project from OpenCores to GitHub, now under wfjm/w11. |
| Jun-2015 | added RH70 + RP/RM disks; TM11/TU10 tapes; now complete mass storage system. |
| Mar-2015 | use Vivado; Artix-7 ports added (for Basys3 and Nexys4); added RL01/RL02 disks. |
| Apr-2013 | new C++/Tcl backend server, w11a designs operate with rlink over USB. |
| Jan-2012 | Cypress FX2 USB controller support added, rlink and config over USB. |
| Dec-2011 | Spartan-6 port of w11a added (for Digilent Nexys3 board). |
| Jul-2010 | OpenCores project w11 created; w11a V0.5 tagged and released. |
| May-2010 | w11a systems ported to Digilent Nexys2 board; lots of cleanup. |
| Sep-2009 | 2.11BSD UNIX boots to multi-user mode on w11a on FPGA. |
| Aug-2009 | UNIX 5th Edition boots on w11a on FPGA. |
| Jun-2009 | Found 11/70MP system manual on bitsavers. Most of IIST implemented. Too early, but fun. |
| Dec-2008 | Finished the last of three 2.11BSD patches, now 2.11BSD boots of a RK05 disk set and runs on a 11/70 without FPP in simh. |
| Mar-2008 | Full system with CPU, cache, and minimal I/O system runs on FPGA. |
| Sep-2007 | rri (rbus+rlink) implemented, w11a runs on FPGA (Digilent S3BOARD). |
| Sep-2006 | CPU and MMU implemented, simple test codes run. |
| Jun-2006 | Re-discovered a pile of PDP-11 manuals in a forgotten box full of old paper work. This triggered the idea, and with simh, ghdl and bitsavers at hand, 2.11BSD as target OS and a 11/74 picture as desktop background it quickly became a project. |