Fig R-1: w11a running on a Digilent S3BOARD board with XC3S1000. The rlink connection is via the RS232 port and a FTDI US232R-100 archived on
cable. The DBB1 kludge card contains a test setup for a FTDI UM232R archived on
module. (wfjm cc-by-4.0)
Fig R-2: Two of four processors of the 11/74 prototype PHEANX, which was used up to the 90's for RSX builds. Earlier the machine was used under the name CASTOR by DEC RSX Engineering in Maynard. Picture courtesy of Dave Carroll.


Long-term goal is to re-create a PDP-11/70mP system. This up to 4 CPU symmetric multiprocessor system was developed in the late '70s by DEC but was never marketed. See article The Never 11's archived on
. A few prototypes were built, see Figure R-2 for a picture of PHEANX/CASTOR. Some documentation has survived, like the preliminary DEC 11/70mP system manual, see also a historical summary. Full SMP support was added around 1980 to the RSX-11M-PLUS V2.0 operating system, see for example the set and remove affinity system calls in the Executive Manual (STAF$ on p 5-193 and RMAF$ on p 5-128).

The 11/70mP was based on the KB11-CM CPU which was a minimal modification of the KB11-C CPU, used in the 11/70, for basic SMP support. The famous 11/74 was based on the KB11-EM CPU with a much larger microstore and commercial instruction set (CIS) support (see Preliminary 11/74 specification). There are no plans in the w11 project to implement CIS, so the long-term goal is a modest 11/70mP and not a full glory 11/74.

Worth noting in this context is that already in 1972 a 16 node SMP system based on PDP-11 CPU's was built by W. Wulf and G. Bell at Carnegie Mellon, the C.mmp, see their paper "C.mmp--A Multi-mini-processor" for the Fall JCC 1972.

Permanent Tasks

Short term (in work)

Mid term

Long term

Maybe term

Nice ideas, maybe they are realized, maybe not


Ports to new boards will be done when interesting products show up. Tempting boards are:

Release plan for w11a

Release  Target Date  Main release goals
V0.80 t.b.d. I/O complete (DEUNA, DZ11, buffered DL11,PC11,LP11)
V0.90 t.b.d. resolve cpu issues; add FPP, CPU complete
V1.00 t.b.d. resolve device and backend issues
V1.10 t.b.d. move ISE designs into legancy branch; VHDL-2008 code base
V1.20 t.b.d. write-back cache
V1.30 t.b.d. multi-CPU systems
V1.40 t.b.d. systems with Maintenance and IO Processor (MIOP; local IO handling)
V1.50 t.b.d. stand-alone systems