- improve documentation, especially Tcl API
- improve verification, e.g. test benches
- resolve known issues
Short term (in work)
- support DDR memory on Arty and Nexys4 DDR
- DEUNA Ethernet; 2.11BSD on w11a on the internet.
- fifo buffered implementation of character devices (DL11,LP11, maybe PC11 too).
- DZ11 terminal multiplexer; classical multiuser operation.
- KW11P: programmable clock (needed for 2.11BSD kernel profiling).
- TOY clock: the time-of-year clock was never part of a 11/70 system, but it is very convenient to have.
- FPP Floating Point Processor: The FPP will be asynchronous, with a more efficient coupling than in the original KB11-C CPU plus FP11-C FPP combination.
- new cache system: now write-back, wider cache lines, suitable to build a 11/70MP multiprocessor system. In contrast to the original 11/70MP a state-of-the-art cache coherence will be implemented.
- configurable CPU: make CPU features build-time configurable, for example to generate stripped down w11a versions optimized as an embedded console and IO processor in larger systems.
- stand-alone system: a system with an additional w11a CPU acting as CIOP (console and IO processor) which can be operated without a backend server.
- CPU throttling: some old code, especially tests with timing loops, has problems on a fast machine....
Beyond long term
- port to ZTEX USB-FPGA Module 2.13. The ZTEX 2.13 combines Atrix-7 and Cypress FX2, and has a fast JTAG over USB, and is therefore a good candidate for 'yet another port'.
- w11p: new CPU with a much improved micro architecture. With micro- and macro-pipelining and a significantly improved CPI, better than the J11. Much faster than the w11a and derivatives, but also significantly higher resource consumption. Will implement, finally, the 11/44 and J11 special instructions (MFPT, MTPS, MFPS, TSTSET, WRTLCK), and make the processor type selectable.
Release plan for w11a
|Release||Target Date||Main release goals|
|V0.80||t.b.d.||I/O complete (DEUNA, DZ11, buffered DL11,LP11)|
|V0.90||t.b.d.||CPU complete (FPP, write-back cache,...)|
Long term goal is to re-create a PDP-11/70MP (aka 11/74) system. This up to 4 CPU symmetric multiprocessor system was developed in the late '70's by DEC, but was never marketed. See article The Never 11's . A few prototypes were build, see Figure R-2 for a picture of PHEANX/CASTOR. Some documentation has survived, like the preliminary DEC 11/70MP system manual, see also a historical summary. Full SMP support was added around 1980 to the RSX-11M-PLUS V2.0 operating system, see for example the set and remove affinity system calls in the Executive Manual (STAF$ on p 5-193 and RMAF$ on p 5-128). Worth to note in this context is that already in 1972 a 16 node SMP system based on PDP-11 CPU's was build by W. Wulf and G. Bell at Carnegie Mellon, the C.mmp, see their paper "C.mmp--A Multi-mini-processor" for the Fall JCC 1972.