Releases
Major releases are labeled with bold tag fields, while minor
releases are labeled with italic tag fields.
The code lines by language evolution is available in section
Statistics.
| Release | Date | commit | README | Comment |
|---|---|---|---|---|
| (0.797) | t.b.d. | planned | oskit update; ouxr update | |
| (0.796) | t.b.d. | planned | dev xxdp | |
| (0.795) | t.b.d. | in work | DEUNA buffer chaining | |
| HEAD | today | - | CHANGELOG | state of master/HEAD, the bleeding edge |
| w11a_V0.794 | 2023-02-09 | 03ef66e | CHANGELOG | asm-11 finalized; mcodes documented |
| w11a_V0.793 | 2023-01-12 | 8fc44a4 | CHANGELOG | w11 CPU xxdp clean; closes #36, #37; ECO- 035, 036, 037, 038, 039, 040 |
| w11a_V0.792 | 2022-10-25 | 9ca20e3 | CHANGELOG | consolidate test bench, ostest; drop Nexys4; cleanups; viv 2022.1; closes #24, #25, #26, #33, #34, #35; ECO- 031, 032, 033, 034 |
| w11a_V0.791 | 2022-04-24 | 7ec5be2 | CHANGELOG | GitHub actions; Vivado 2020.1; ostest; finalize Nexys A7 (closes issue #16) |
| w11a_V0.79 | 2019-07-27 | 1742dfa | CHANGELOG | use SPDX license tags; Vivado 2019.1; Coverity defect free; TM11 odd record length (closes issue #8) |
| w11a_V0.78 | 2019-06-01 | 279fff9 | CHANGELOG | add M9312 boot prom and DZ11 serial port multiplexer |
| w11a_V0.77 | 2019-04-28 | 0bdd9f1 | CHANGELOG | buffered LP11,PC11,DL11; ECO- 030 |
| w11a_V0.76 | 2019-02-16 | 5a3c40a | CHANGELOG | DDR memory support for Arty A7 and Nexyx4 DDR |
| w11a_V0.753 | 2018-12-29 | b8dfa6d | CHANGELOG | add KW11-P clock, CPU performance counters, 'ram:' disk |
| w11a_V0.752 | 2018-08-26 | 40d4868 | CHANGELOG | Add Digilent Arty S7 support; only simulation tested ! ; Vivado 2017.2 |
| w11a_V0.751 | 2018-08-10 | f78b571 | CHANGELOG | Add Digilent Cmod A7 support; Vivado 2017.1; add Unix 7th oskit |
| w11a_V0.75 | 2017-06-04 | 5d3504b | CHANGELOG | DEUNA Ethernet interface added (functionally restricted); 2.11BSD with full networking |
| w11a_V0.742 | 2017-01-07 | a6bbe47 | CHANGELOG | Fixes for Vivado 2016.4; added w11 shell; Preliminary Digilent Nexys4 DDR support; two minor CPU fixes, ECO- 028, 029 |
| w11a_V0.741 | 2016-12-23 | 51cb648 | CHANGELOG | moved from OpenCores to GitHub; docu converted to markdown |
| w11a_V0.74 | 2016-10-15 | 5983b0b | README | upgraded CRAM controller; new test bench driver |
| w11a_V0.73 | 2016-06-26 | 2b5cfb7 | README | Code cleanup for Vivado, more xsim support; Size-configurable cache, better w11a performance |
| w11a_V0.72 | 2016-03-19 | e1479d4 | README | port of w11a to Digilent Arty A7; support for XADC; initial Vivado xsim support |
| w11a_V0.71 | 2015-12-30 | 677773d | README | Add CPU debug and monitoring units (dmhbpt,dmscnt,dmcmon); ECO- 027 |
| w11a_V0.70 | 2015-06-21 | f514906 | README | from 0.6 -> 0.7; revised rbus protocol; Vivado support; Nexys4 and Basys3 port; RP/RM and RL11 disk and TM11 tape support |
| w11a_V0.66 | 2015-06-05 | 24fde41 | README | Support TM11/TU10 tapes |
| w11a_V0.65 | 2015-05-14 | 4a032e9 | README | Support RH70 + RP/RM big disks |
| w11a_V0.64 | 2015-03-09 | e91847f | README | Support for Vivado; port of w11a to Digilent Basys3 and Nexys4; RL01/RL02 disks |
| w11a_V0.63 | 2015-01-04 | dde49d5 | README | w11a rbus interface and C++/Tcl backend now use rlink v4 features, much reduced number of round trips |
| w11a_V0.62 | 2014-12-20 | d87ac86 | README | Introduced rlink protocol v4 (see README_Rlink_V4) |
| w11a_V0.61 | 2014-08-10 | 093d540 | README | Bugfix for DIV instruction; ECO- 026 |
| w11a_V0.60 | 2014-06-06 | 46331ca | README | from 0.5 -> 0.6; revised ibus and rbus protocol; backend server rewritten; Nexys3 port; Cypress Fx2 support; LP11,PC11 support |
| w11a_V0.581 | 2014-05-29 | 4732555 | README | Fixes for ISE 14.7; Spartan-6 CMT support; more man pages |
| w11a_V0.58 | 2013-05-12 | 200ba69 | README | LP11,PC11 support added; old backend retired; operating system kits re-organized |
| w11a_V0.57 | 2013-04-27 | b06cbef | README | w11a systems with rlink over USB on Nexys2 and Nexys3 boards |
| w11a_V0.562 | 2013-04-13 | 99de989 | README | Phase 2 of new C++/Tcl backend, add cpu and first device support; add asm-11 assembler |
| w11a_V0.561 | 2013-01-06 | 29d2dc5 | README | Add bugfixes, Cypress FX2 simulation model, and test designs for Nexys3 and Atlys boards |
| w11a_V0.56 | 2013-01-02 | cbd8ce3 | README | Add Cypress FX2 USB interface controller; FX2 firmware supporting jtag access and data transfer; test system for rlink over USB verification |
| w11a_V0.55 | 2011-12-23 | f6775f7 | README | Add xon/xoff (software flow control) support to serport library; Add test design for serport verification |
| w11a_V0.54 | 2011-12-04 | f2d0f39 | README | Add Digilent Nexys3 port of w11a |
| w11a_V0.532 | 2011-11-20 | d76323e | README | Add test design for 'human I/O' interface; migrate to use numeric_std |
| w11a_V0.531 | 2011-09-12 | e152956 | README | Prepare upcoming support for Spartan-6 (Nexys3 and Atlys) and Cypress FX2 USB (Nexys2/3 and Atlys) |
| w11a_V0.53 | 2011-04-17 | 0f28def | README | Introduced new backend written in C++ and Tcl. Phase 1 with functionality to execute simple test benches |
| w11a_V0.52 | 2011-01-02 | c3d40ba | README | Introduced rbus protocol V3; reorganize rbus and rlink modules, many renames |
| w11a_V0.51 | 2010-11-28 | 16ce5b2 | README | Introduced ibus protocol V2; Nexys2 systems use DCM; sys_w11a_n2 now runs with 58 MHz |
| w11a_V0.50 | 2010-07-23 | 3266c23 | README | Initial release; w11a CPU core; basic set of peripherals; KW11-L, DL11, LP11, PC11, RK11/RK05; complete systems for Digilent S3BOARD and Nexys2 |