Test Benches

The project contains self-checking test benches for several components, the w11a core as well as for the whole systems under

  rtl/vlib/serport/tb              UART and autobauder
  rtl/vlib/rlink/tb                remote register interface
  rtl/w11a/tb                      w11a core
  rtl/sys_gen/w11a/arty/tb         w11a_arty system
  rtl/sys_gen/w11a/artys7/tb       w11a_as7 system
  rtl/sys_gen/w11a/basys3/tb       w11a_b3 system
  rtl/sys_gen/w11a/cmoda7/tb       w11a_c7 system
  rtl/sys_gen/w11a/nexys2/tb       w11a_n2 system
  rtl/sys_gen/w11a/nexys3/tb       w11a_n3 system
  rtl/sys_gen/w11a/nexys4/tb       w11a_n4 system
  rtl/sys_gen/w11a/nexys4d/tb      w11a_n4d system
  rtl/sys_gen/w11a/s3board/tb      w11a_s3 system
  rtl/sys_gen/w11a/tb              common files for system tests

See w11a_tb_guide.md for detailed instructions to run these test benches.

Test Programs

The CPU core, as well as the peripherals, have been verified in GHDL simulation and in FPGA with test programs. The list of acceptable implementation differences as well as a list of issues to be resolved in upcoming revisions are summarized in w11a_known_issues.md.