Directory Structure of the Repository

Some conventions used throughout the project:

The following list gives only the key directories, inspect the project to see all:

doc Documentation
rtl VHDL sources
rtl/bplib - board and component support libs
rtl/bplib/arty - for Digilent Arty A7 board
rtl/bplib/artys7 - for Digilent Arty S7 board
rtl/bplib/basys3 - for Digilent Basys3 board
rtl/bplib/cmoda7 - for Digilent Cmod A7 board
rtl/bplib/fx2lib - for Cypress FX2 USB interface controller
rtl/bplib/issi - for ISSI parts
rtl/bplib/micron - for Micron parts
rtl/bplib/mig - for Vivado MIG cores
rtl/bplib/basys3 - for Digilent Basys3 board
rtl/bplib/nexys2 - for Digilent Nexys2 board
rtl/bplib/nexys3 - for Digilent Nexys3 board
rtl/bplib/nexys4 - for Digilent Nexys4 board
rtl/bplib/nexys4d - for Digilent Nexys A7 board
rtl/bplib/nxcramlib - for Numonix CRAM (on Nexys2,3,4)
rtl/bplib/s3board - for Digilent S3board
rtl/bplib/sysmon - for Series-7 XADC
rtl/ibus - ibus devices (UNIBUS peripherals)
rtl/sys_gen - top level designs
rtl/sys_gen/tst_mig - designs for a MIG core tester
rtl/sys_gen/tst_rlink - designs for a rlink tester
rtl/sys_gen/tst_rlink_cuff - designs for a rlink over FX2 tester
rtl/sys_gen/tst_serloop - designs for a serial link tester
rtl/sys_gen/tst_snhumanio - designs for a human IO tester
rtl/sys_gen/tst_sram - designs for a sram tester
rtl/sys_gen/w11a - designs for w11a SoC
rtl/sys_gen/w11a/arty - w11a SoC for Digilent Arty A7
rtl/sys_gen/w11a/arty_bram - w11a SoC for Digilent Arty A7 (BRAM only)
rtl/sys_gen/w11a/artys7 - w11a SoC for Digilent Arty S7 !only simulated!
rtl/sys_gen/w11a/artys7_bram - w11a SoC for Digilent Arty S7 (BRAM only) !only simulated!
rtl/sys_gen/w11a/basys3 - w11a SoC for Digilent Basys3
rtl/sys_gen/w11a/cmoda7 - w11a SoC for Digilent Cmod A7
rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexys2
rtl/sys_gen/w11a/nexys3 - w11a SoC for Digilent Nexys3
rtl/sys_gen/w11a/nexys4 - w11a SoC for Digilent Nexys4
rtl/sys_gen/w11a/nexys4d - w11a SoC for Digilent Nexys A7
rtl/sys_gen/w11a/nexys4d_bram - w11a SoC for Digilent Nexys A7 (BRAM only)
rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3board
rtl/vlib - VHDL component libs
rtl/vlib/comlib - communication
rtl/vlib/genlib - general
rtl/vlib/memlib - memory
rtl/vlib/rbus - remote-register-interface - rbus
rtl/vlib/rlink - remote-register-interface - rlink
rtl/vlib/serport - serial port (UART)
rtl/vlib/simlib - simulation helper lib
rtl/vlib/xlib - Xilinx specific components
rtl/w11a - w11a core
tools helper programs
tools/asm-11 - pdp-11 assembler code
tools/bin - scripts and binaries
tools/dox - Doxygen documentation configuration
tools/exptest - configuration files for ostest etc
tools/fx2 - Firmware for Cypress FX2 USB Interface
tools/gwstart - environment for the gwstart command
tools/make - make includes
tools/man - man pages for scripts in tools/bin
tools/mcode - miscellaneous stand-alone codes for system tests
tools/oskit - setup files for Operation System kits
tools/simh - configuration files for SimH pdp11 simulator
tools/src - C++ sources for rlink backend
tools/src/librlink - basic rlink interface
tools/src/librlinktpp - C++ to tcl binding for rlink interface
tools/src/librtcltools - support classes to implement Tcl bindings
tools/src/librtools - general support classes and methods
tools/src/librutiltpp - Tcl support commands implemented in C++
tools/src/librw11 - w11 over rlink interface
tools/src/librwxxtpp - C++ to tcl binding for w11 over rlink iface
tools/sys - udev rules for USB device handling
tools/tbench - w11 test bench, tcl based
tools/tcode - w11 test bench, mac based
tools/tcl - Tcl sources for rlink backend
tools/tests - test programs
tools/vivado - scripts for Xilinx Vivado
tools/xxdp - startup and patch scripts for xxdp test execution